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50: bit 6 set to 1 (mem single write cycle) or 0 in w2k
52: bit 7 set to 0 (dram time delay set to 0)
52: bit 6 set to 1 (single read allocation)
52: bit 4 set to 1 (sync cpu-dram mode)
55: bit 2 set to 0 (disable res bit for data read dram)
56: bit 7..6 set to 11 (6 clocks)
58: bit 7..6 set to 00 (2 clocks)
58: bit 5..4 setting from 01 to 00 crashes (from 3 clocks to 2 clocks) !!!! never succeeded once here
5D: bit 4 set to 1 (dram write retire rate = x-1-1-1)
5D: bit 3 set to 0 (cas latency = 2 clocks)
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